Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits

The logic behavior and performance of ECL gates under a set of defect models are examined. These are compared with equivalent set of BiCMOS and CMOS gates. It is found that logical fault testing is inadequate for obtaining a sufficiently high fault coverage, e.g., 79% for ECL versus 54% for BiCMOS and 69% for CMOS equivalent gates. Performance degradation faults such as delay, current and Voltage Transfer Characteristics (VTC) or Noise Margin (NM) faults are analyzed as applied to these gates. It is shown that logical fault testing with delay fault testing yields the highest fault coverage for BiCMOS and CMOS gates (around 95%). However, for equivalent ECL gates to attain a fault coverage of around 98%, both logical and NM fault testing have to be used. mitter Coupled Logic (ECL) devices operate out of saturation which eliminates transistor storage time as a speed limiting characteristics, thus permitting very high speeds of operation [1]. Conventional ECL technology provides system propagation delays of the order of 300 to 500 ps. However, the price paid for such speeds is very high power dissipation (more than 2 mW per gate) [2-4]. With recent advances in technology such as BIT1 [2], it becomes possible to fabricate ECL devices that take about 1/20th the area of conventional ones, with speeds comparable to the fastest ECL transistors and consuming only 1/10th of the power. As a result of the low power, high speed and relatively high density, ECL technology is used in the design of Application Specific integrated Circuits (ASICs) which are frequently utilized in applications demanding the highest circuit performance. It is also important to mention that ECL technology is currently used in BiCMOS processes, whereby ECL circuit islands embedded in BiCMOS circuits are required for critical path regions and for high speed operations. With the increase in performance and complexity of ECL circuits, the testability issue becomes very important in the design process. The issue of fault modeling of ECL gates has been addressed in [3-6]. The fault models presented in [3-5] only consider logical faults; however, performance degradation faults, which could not be characterized by a failure in the device logic, are not discussed. For example, ECL high and low level noise margins are small (around 0.3V), and these make the circuits susceptible to noise or fluctuations that inevitably appear on the power supply line. In the presence of defects, the noise margins …